Gerri prefers

This is not a picture of a room because I have not uploaded a picture of a pink wall with a single pixel gold-sequined smudge  to the internet and did not spoil it for everyone. Physical might and threats of “we will come and find you” are no match for a brain cell and testdisk.

Stellaris SSI EOT Interrupt

I’ve recently been writing code for the TI Stellaris cortex-m3 line of parts (Both the lm3s9b96 and the lm3s9l71). One particular facet of the project calls for Interrupt driven SPI comms to a slave device. Amazingly, all of the example and project code shipped by TI is for polled/blocking interaction with the SSI peripheral.

Generally, I have been using the reference code and the well commented driver library to find my way around the peripherals. I have only really referred to the actual datasheet to find out what’s actually there and observe any caveats. Now that I actually needed the datasheet for something, I found it woefully lacking in the SSI interrupts area. In particular the EOT (End of Transmission) interrupt.

The EOT Interrupt appears to have been an addition at some point in the devices life and feels a bit bodgy. It does not really seem to conform to the style that all the other interrupts have. This is compounded by no description of operation in the text of the data sheet.

After a *lot* of messing about writing small test cases, I got the interrupt firing in a useful way. Example code below.

The key things are:

• Set the SSI_CR1_EOT bit in SSI_O_CR1.

This changes the TXFF interrupt into the EOT interrupt

• Enable the TXFF interrupt by setting its interrupt mask bit

Don’t be fooled (I was), this doesn’t mean the TXFF interrupt flag is now the EOT flag(this seems likely from the register layout).

• In the interrupt handler, check the RNE bit of the SSISR (ssi status reg)

If this set, read from the RX FIFO until it clears. This also appears to clear the EOT interrupt so the interrupt does not hit as soon as you return from the handler.

With hindsight, this doesn’t seem too surprising but it was very non-obvious as I tried to get it going.

Warning this may all be a load of tosh but it seems to work ok for me.

Peripheral init:

    SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOH);
SysCtlPeripheralEnable(SYSCTL_PERIPH_SSI1);
ROM_GPIOPinTypeGPIOInput(GPIO_PORTH_BASE,GDO0_PIN);

GPIOPinTypeGPIOOutput(GPIO_PORTH_BASE,SCK_PIN);
GPIOPinTypeGPIOOutput(GPIO_PORTH_BASE,MOSI_PIN);
GPIOPinTypeGPIOInput(GPIO_PORTH_BASE,MISO_PIN);
GPIOPinTypeGPIOOutput(GPIO_PORTH_BASE,CSN_PIN);

GPIOPinConfigure(GPIO_PH4_SSI1CLK);
GPIOPinConfigure(GPIO_PH7_SSI1TX );
GPIOPinConfigure(GPIO_PH6_SSI1RX );
GPIOPinTypeSSI(GPIO_PORTH_BASE,SCK_PIN | MISO_PIN |MOSI_PIN);

/* Dont use ROM_ see errata */
SSIConfigSetExpClk(SSI1_BASE, SysCtlClockGet(), SSI_FRF_MOTO_MODE_0,
SSI_MODE_MASTER, 1000000, 8);
SSIEnable(SSI1_BASE);

while(SSIDataGetNonBlocking(SSI1_BASE, &ulTemp)) /* empty buffer */
{
}

/* switch to interrupt driven SPI */

SSIIntDisable(SSI1_BASE, SSI_TXFF | SSI_RXFF | SSI_RXTO | SSI_RXOR );
SSIIntClear(SSI1_BASE, SSI_TXFF | SSI_RXFF | SSI_RXTO | SSI_RXOR );

HWREG(SSI1_BASE + SSI_O_CR1) |= SSI_CR1_EOT; /* switch tx interrupt to eot int */

SSIIntEnable(SSI1_BASE, SSI_TXFF ); /* SSI_TXFF | SSI_RXFF | SSI_RXTO | SSI_RXOR  */

ROM_IntEnable(INT_SSI1);

IntMasterEnable();
UARTprintf(“End init\n”);

And the interupt handler:

void SSI1IntHandler(void)
{
volatile unsigned long status=0;
unsigned long data=0;

status = SSIIntStatus(SSI1_BASE, true);
SSIIntClear(SSI1_BASE, SSI_TXFF | SSI_RXFF | SSI_RXTO | SSI_RXOR );

while( HWREG(SSI1_BASE + SSI_O_SR) & 4)
{

SSIDataGetNonBlocking(SSI1_BASE, &data);
UARTprintf(“|got %x “,data);
}
/* Check other flags here if needed */
}

TI Stellaris USB host speed (MSC)

Ive been looking at using the TI Stellaris implementation of the cortex-M3. The application I am aiming for needs a modest but guaranteed bandwidth to disk. After lots of trawling the web I eventually decided to try Ti support:

Brief description of your request: What data rate can one expect from a stellaris cortex-M3, probably 5000 series into a USB attached hard drive Using the Stellarisware usb libs. Also what is the processor load like in that situation.

Many thanks.

A chap phoned back the following week (!) by which point I had given up on them. He was calling from a really noisy call centre by VOIP. After a very short conversation in which I repeated my question he said “Oh the line is really bad, can I email you.” Firstly that’s not my fault, get a better connection. Secondly, why did this cease to matter when I mentioned the volume that I was planning to use. He said he would pass it up.

Eventually I got a reply:

Thank you for contacting Texas Instruments. Your request has been received and Service Request number ###### has been assigned to your inquiry.

I am sorry for the delay of the response.

Right now we do not have any benchmark for the StellarisWare USB stack.

If you want to do this your self you can try the EK-LM3S3748, here you will have a demo example showing the functionality you want to benchmark. See link for the evaluation kit.
http://www.ti.com/tool/ek-lm3s3748

Please here be aware that the StellarisWare code is not optimized for speed and rewriting the drivers could also improve the speed of the transfer and the device you looked at can run at 80MHz and not 50MHz as the evaluation kit.

Do not hesitate to contact us again if you have any further specific questions.

Kind regards,

[Guy number twos name]
Application Support Engineer
Texas Instruments Deutschland GmbH
European Customer Support Center
http://www-k.ext.ti.com/sc/technical-support/pic/euro.htm

I’m quite sure that this isn’t the guy I spoke to on the phone he is certainly more polite.
I find it quite surprising that TI don’t even have an idea of what it can do. Surely they must test their example code?

Either way pretty unsatisfactory, It of course makes me start thinking of conspiracy theories, is the peripheral really slow and they don’t dare say? It wouldn’t be the first time, see Atmel and the SAM9G USB.

So come on TI, do you fancy sending me a dev board so I can work it out for myself? Lets face it I’m not paying £75 for something that appears to be not upto scratch.

What exactly do you mean by “secure server”

from: customerservice@eonenergy.com

The email you’ve attempted to send has not been delivered.

Please resend your comments using the link provided to http://www.eonenergy.com/At-Home/Contact.

We’ve redirected you to the website to guarantee the security of your information, as any information you send to us will be via a secure server.

Please don’t reply directly to this email.

Kind Regards
E.ON

Mechanical failure whilst cycling.

Yesterday, whilst cycling to work I suffered a mechanical failure, fault isolation only took about 45 min. Debug included below. Sadly farnell and rs do not stock spares.

Better res here

Rihannas LED dress

After relaxing few days away, Moritz gave me a call with an offer of a simple assembly job. Deadline about 2 weeks away a few thousand components and a bit of software. Its now just under 6 weeks and I’m remarkably still going.

So far the project has included building two ‘video capable’ led covered dresses and their support equipment. This included a few thousand lines of code, 32 PIC18f46k20 microcontrollers (This is a blog post in its self but to summarize, PIC’s are rubbish), 15 same day couriers, 20 Farnell orders (Did you know you can buy on-line at Farnells website) approximately 4500 red LED’s and very little sleep. The first dress these was finished on the road with the Last girl on earth tour. For the second dress I dragged Jeff and Justyn into the giant food processor that this project became. There is a third dress planned as a replacement for the first.

When more of the confetti has settled I will write a more verbose post with some of the cool stuff that happened for now I would like to thanks everyone who helped directly and indirectly, particularly: Jeff, Justyn, Steve, Pippa, Faye, Rob, Franzi and Moritz

Here are some pictures:

This is currently the best video that has made it to youtube, its a start…

Ah no wait, RS still suck

Thank you for choosing RS Components. A representative will be with you shortly.
You are now connected with Donna.
Donna: Hello, you’re chatting with Donna, an RS Sales Specialist. May I take your name please?
You: Morning, im Tom
Donna: Hello Tom how can I help you today?
You: Please could you advise on the availability of 496-6780
(appx 5min wait)
Donna: Tom I am happy to help you this morning. can I ask how many you were looking for and are you looking for delivery or collection from one of our trade counters.
You: It depends how many are available, Ideally for delivery but i could arrange to collect them from a trade counter if necessary
(appx 5min wait)
Donna: Tom how many were you looking for and I can check for you what is available.
You: well If i have to invent a number, do you have 1300?
(appx another 5min wait, preparing for a binary search)
Donna: Let me see what I can do for you.
Donna: Tom we are showing that we have 90 in stock at present.
You: Thankyou, have a good day
Donna: Thank you for chatting with me today. RS really values your feedback. Please click the “End Chat” button at top right of chat box to answer a few questions about your experience with us today.
(STANDBY!)

2 days of debugging

Turns out that 0xaa (10101010) Only confirms correct endianness when your polarity is correct! It looks correct when inverted in time and voltage.

--- a/firmware/test4/fpga.c
+++ b/firmware/test4/fpga.c
@@ -46,11 +46,11 @@ void fpga_prog(uint8_t* block, uint8_t blen){
 //     IOE = block[0];
        if((fpga_state==READY) || (fpga_state==MIDPROG)){
                for(position=0;position<blen;position++){
-                       for(byte_pos=1 ; byte_pos!=0 ; byte_pos=byte_pos<<1){
+                       for(byte_pos=0x80 ; byte_pos!=0 ; byte_pos=byte_pos>>1){
                                if((block[position] & byte_pos)>0)
-                                       DILO();
-                               else{
                                        DIHI();
+                               else{
+                                       DILO();
                                }
                                bit_delay(10);
                                CLKHI(); /* min setup time 5ns so should be safe */

Autobus

Until now the quest for self-driving cars has never really grabbed me, yes it would be quite cool to be able to sleep on the way to work etc. It has however just occurred to me that there is a significant use for this technology that is always overlooked. Replacing that great institution, the small minded bus driver.

Its currently 0305 in the morning, I have been stood around in the cold for longer than I care to think about. It is of note that the bus is functioning perfectly, thus the common expression “the bus was late” Is infarct incorrect. To be precise, the Bus driver is late… He is not gaining ground either, before I had even stepped foot on the coach he had started telling me what I can and cant do. I normal wax lyrical about how good the Oxford tube coach service is. Today it is however let down by MC Dave whos in flight announcement felt the need to define the the term legal requirement (Seatbelts) as meaning not an option. Soon we will have driver-less buses and 49% of the misery of coach travel will be removed. Just imagine the beauty!

A report on BBC news tells of a bus driver shortage “crisis” due to attacks on bus drivers. Apparently this is being addressed by fitting CCTV. I feel this is missing the point. Surely the main reason they are being attacked in the first place is that the majority are grumpy small minded little control freaks. It would be highly inappropriate of me not to point out that I have met some absolute gems who have made travel pleasant, its a shame there is no simple feedback mechanism whereby they can be rewarded whilst the guy driving me right now is offered employment in the prison service.

Bring on the automation!

Gigabyte P55MUD2.F4/GA-P55M-UD2 checksum

To cut a long and dull story short, I bought the parts for a new PC and have been trying to get it stable for about a month, so far….

Part of this saga was re-flashing the motherboard bios. It has a simple boot loader during POST to do this. The boot-loader called qflash gives a checksum for the binary file it has loaded. I could not find the expected value for this anywhere so filled in a technical support form and braced for the mysery.

Question – 844406
From : Tom [*********]
Sent : 11/30/2009 19:50
Question : When upgrading the bios, I was given a checksum by the qflash utility. I cannot find anywhere what the correct checksum is. Please can you confirm this value for f4 and f5 bios updates.
Many thanks

Answer – 844406
Answer : Hi,

Please ensure you have the correct BIOS update.

http://www.gigabyte.eu/Support/Motherboard/BIOS_Model.aspx?ProductID=3165

Please try to reset the CMOS –
1) Disconnect the power cord from the power supply. Remove the CMOS battery (the flat silver disk) from the motherboard using a srew drive or similar implement. Leave it out for a minute or two, then replace it and power on the system. The BIOS settings should have been reset, allowing the computer to boot.
2) Go into the BIOS – “Load optimized default”
3) Save settings and exit.
4) If this doesn’t work then try “Load Failsafe default”

UUUUGH! Is this automated or are they stupid?

Question – 848338
From : Tom [ gigabyte@…]
Sent : 12/8/2009 20:11
Question : This is not an answer to the question I have asked….
More to the point how am I supposed to know if I have the correct bios update (As you suggest) without the checksum.

So more precisely:
What is the valid checksum in qflash for you bios f4 and f5 on a GA-P55M-UD2(rev. 1.0).
I believe this will be a 4 digit numeric or alphanumeric value…

Regards,

Answer – 848338
Answer : Hi,

We can provide checksum for you but before the providing, please give us more information.

– What is “I was given a checksum by the Qflash utility”? Is that you pressing F8 in bios, entering Qflash menu and get checksum error message or other condition?

– Please also confirm the bios resource. We want to make sure the bioses for this model.

– Also check the original bios on your P55M-UD2. Did you ever flash bios successfully on this motherboard?

Sounds like stalling to me.

Question – 849152
From : Tom [ gigabyte@….]
Sent : 12/10/2009 07:30
Question : I refer to wanting to flash the bios, to the latest version. After the qflash utility[1] has loaded the binary file, extracted from the exe provided on your website[2] the qflash utility gives a 4 digit checksum and asks for confirmation before writing to EEPROM. To make use of this check, one needs to know the correct value.

This is the checksum for the bios firmware, not the variables held in ram.

I enquire about both the f4 and f5 checksums since I have flashed a system to f4 and wish to verify it was correct. Also to flash a further motherboard to f5.

Many thanks,

[1]Accessed by pressing <END> during POST – See p68: http://www.gigabyte.com.tw/Support/Motherboard/Manual_Model.aspx?ProductID=3165#anchor_os

[2] http://www.gigabyte.com.tw/Support/Motherboard/BIOS_Model.aspx?ProductID=3165#anchor_os

Answer – 849152
Answer : Hi,

Here they are:

P55MUD2.F4 – 7400h

P55MUD2.F5 – 2D00h

This took 10 days to get and answer, why cant it just be in the bios download, a text file would do! Also why is the bios in a self extracting .exe file?? Whilst this appears to be a well spec’ed board, I don’t think I will be buying Gigabyte again, I have been generally unimpressed by them in more areas than this.